As is known and shown by way of example in FIG. 1, a flash memory array 1 comprises a plurality of flash cells 2 disposed on lines and columns, in which the gate terminals of the cells 2 disposed on one and the same line are connected to a respective word line 3, the drain terminals of the cells 2 disposed on one and the same column are connected to a respective bit line 4 and the source terminals are generally connected to ground. The word lines 3 are connected to a row decoder 5 and the bit lines 4 are connected to a column decoder 6 which receive respective address and control signals from a control unit 7 which permits the selection, from time to time, of a single word line 3 and a single bit line 4 and the biasing of the cell 2 connected to the word line and to the bit line selected at the operating voltages provided.
In particular, a cell 2 may be read by connecting the selected word line 3 to an external voltage V.sub.G of preset value (such as 8-9 V) and forcing a biasing current I.sub.f into the selected bit line 4. Keeping the selected cell in linear region, the following equation applies: EQU I.sub.f =K*(W/L)*[(V.sub.G -V.sub.th)-V.sub.DS /2]*V.sub.DS(1)
in which K is a constant associated with the production process. W/L is the dimensional width/length ratio of the cell, V.sub.th is the threshold voltage of the cell (or the minimum voltage to be applied between the gate and source terminals of the cell so that it begins to conduct current) and V.sub.DS is the drain/source voltage drop of the cell. In (1) the term K*(W/L)*V.sub.DS =GM.sub.f represents the transconductance (gain) of the cell and the term (V.sub.G -V.sub.th) represents the overdrive of the cell.
By suitably biasing the cell, the drop V.sub.DS is constant and the term V.sub.DS /2 is negligible with respect to the overdrive (V.sub.G -V.sub.th); consequently, in this state the current I.sub.f flowing through the cell depends linearly on the threshold voltage, V.sub.th.
During writing (programming) of the cell, the latter is selected by biasing the selected word and bit lines at respective preset programming voltage values. Writing takes place due to the phenomenon of hot electron injection, whereby a high voltage supplied to the drain terminal of the cell to be written causes an increase in the velocity of the electrons and some of them achieve sufficient energy to overcome the barrier of a tunnel oxide. By forcing on the gate terminal a voltage which is higher than on the drain terminal, the electric field thus created accelerates the electrons through the layer of oxide which separates the channel region from the floating gate region and permits the trapping of those electrons inside the floating gate region. The memory cell modifies its threshold voltage because of this trapping of the electrons.
By its nature, the phenomenon of hot electron injection is not controlled and not repeatable with accuracy; consequently, at the present time, during programming, the cell is read several times for determining the threshold voltage reached (verify phase).
This procedure is far from optimal, however, in view of the long periods of time required because of the need to interrupt programming, measure the threshold level reached and supply a new programming pulse. To overcome these problems for EEPROM memory cells, a system of programming and simultaneous verification of the programming has already been proposed (see U.S. Pat. No. 5,422,842: U.S. Pat. No. 5,495,442 and U.S. Pat. No. 5,532,964 for example) which consists of measuring the current flowing through the cell during programming and comparing it with a reference current; as soon as the measured current becomes equal to or lower than the reference current, programming is interrupted.